Integrated circuit communication, chip to chip, relies upon good input-output (I/O) signal integrity. One significant characteristic of an I/O driver circuit that affects the input-output (I/O) signal integrity is its output impedance with respect to the signal line impedance. Also, variations of both the I/O driver circuit impedance and, e.g., the card impedance often become limiting factors in attaining high speed chip to chip communications with good signal integrity. In general, to maximize the transfer of power in a signal, the output impedance of an output driver circuit should match the input impedance of the transmission media connected to the output driver circuit, such as an electrical cable or another circuit or card.
Various factors that can result in variations of the output impedance of an I/O driver circuit include the process technology itself, along with the operating temperature range and the voltage range for the system. Without attempting to control these factors through some calibration scheme, variations in the output impedance with current state-of-the-art CMOS technology will significantly impact performance. However, current calibration schemes for a transmission driver, which seek for example to maintain a 50 ohm target output impedance, tend to consume significant area and are subject to leakage.